Scripting, Floor-Planning, AI tools, Cadence, RTL2GDS flow, Chip Finishing, flow automation, Physical Verification, Synthesis, Physical Design, Power Distribution, Metal Dummy Fill, Synopsys, Place And Route, Clock Tree Synthesis

Asic Physical Design, PPA targets, Flow definition, Chip-level PD closure, Tapeout readiness, EDA vendor relationships

routing, Signal Integrity, CTS, floorplanning, Timing Closure, IR EM and variability analysis, Placement, low-power design, ASIC SOC physical design implementation, Physical Verification

redhawk , power integrity , Perl scripting, Debugging, Tcl, place-and-route, power network planning, system-level floorplanning, low-power design methodologies, Calibre, Innovus, VLSI logic design, Timing Closure, reliability EM IR analysis, Clock Tree Synthesis

redhawk , power integrity , Debugging, Tcl, Perl scripting, power network planning, low-power design methodologies, reliability EM IR analysis, place-and-route, VLSI logic design, system-level floorplanning, Calibre, Innovus, Timing Closure, Clock Tree Synthesis

Tcl, Verilog, Python, Perl, Clock Tree Synthesis, object-oriented programming, Place And Route, EDA Tools, floorplanning, VHDL, RTL-to-GDSII implementation, Synthesis, Timing Closure