Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions

DDR, Pcie, Verilog, Ethernet, Python, Cadence Incisive, UCIe, Uvm, Synopsys VCS, formal verification, VHDL, Modelsim

C, Perl, Verilog, Shell scripting, Python, Tcl, UVM assertions, systemverilog, SVA

Pcie, Perl, Python, System Verilog, Tcl, CHI, SMMU, assertion-based verification, Uvm, Coresight, Axi, coverage-driven testing, CXL, SVA

Embedded C, Pcie, Perl, Verilog, Debugging, Python, Tcl, ASIC Design Flow, ONFI, systemverilog, hardware bring-up, Validation, LPDDR6, LPDDR5

semiconductor ip , Silicon Validation, systemverilog, Uvm, SOC design, ip design, Simulation, Emulation, Dft, Design For Testability, Ate, Semiconductor, semiconductor design, Design Verification

power optimization , Noc, Networking, Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, High-Level Synthesis, cdc, power analysis, Peripheral Subsystems, Formal Verification Methodology, Shell-scripting, Synthesis, Timing Closure, RTL Coding, Micro-architecture Development

performance verification of ASICs, ASIC standard interfaces, verification components, formal tools, Design Verification, assertion-based verification, Uvm, systemverilog, memory system architecture