Tcl, Python, Rtl Design, logical physical synthesis, chip sign-off timing, Cadence Genus, Logic Equivalence Checking, DC PrimeTime, Cadence Cerebrus, Logic Synthesis, Innovus, Synopsys FC.ai, Tempus, AI driven EDA capabilities, formal verification, Synopsys Fusion Compiler, Synthesis, formal verification, Timing Closure, Physical Synthesis, hierarchical optimization, Synopsys Design Constraints SDC

Functional Design, Problem Solving, Design For Safety and Reliability, Mechanical Design, Electromechanical Engineering, Computer Aided Design, Electrical Safety

Technical Leadership, Unit Testing, Integration Testing, Java Spring, Java, Angular Js, Agile Scrum, Databases, Maven, Microservices, Technical Documentation, selenium, Automated Testing, Design Patterns, FastAPI, shell scripting, python, Sql, Hibernate, data structures, Flask, remote collaboration, object-oriented principles, Persistence Frameworks

GAA (Gate-All-Around, PDK enablement, Planar MOSFETs, Spice model understanding, Foundry PDK enablement, Semiconductor technology analysis, CMOS device physics, Design Automation, Parasitic Extraction, Physical verification decks, Process design interaction, Electrical studies, Cadence-based tool suites, Automation methodology, Co-optimization of PDK components, FinFETs