Vcs, Perl, Verilog, Matlab, Python, Tcl, ALLEGRO, Power Integrity Modeling, Hspice, Simulink, Spectre, Analog and Mixed Signal AMS simulations, Ansys Siwave, Simplis, Primesim, VerilogA, Simulation, Sigrity, Cadence Virtuoso, hfss

Usb, C, Pcie, Verilog, Networking Protocols, Ethernet, Python, high-speed interfaces, Palladium, systemverilog, emulation methodologies, Zebu, Protium

Aws Services, Data Migration, Data Modeling, Python, Sql, ETL ELT pipelines, data quality best practices

Verilog, Static timing analysis, Pcie, Timing closure methodologies, Synthesis, AMBA-AXI, systemverilog, Lint CDC RDC analysis, Power methodology development, Rtl Design

Embedded C, Pcie, Perl, Verilog, Debugging, Python, Tcl, ASIC Design Flow, ONFI, systemverilog, hardware bring-up, Validation, LPDDR6, LPDDR5

Perl, Verilog, Python, Tcl, Circuit Design, Dc, ICC, Electrical Checks, systemverilog, Innovus, Physical Verification, Physical Design, Synthesis PnR, Genus, Deep Submicron Technology, device physics

Design Verification, innovus, icc