Shell, C, Perl, Verilog, Python, Tcl, EDA Tools, UVM methodology, systemverilog

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

System Verilog, Uvm

C, Test Plans, Polymorphism, Vcs, Inheritance, shell scripting, Verilog, Oop Concepts, Python, waveform analyzers, Cadence simulators, AMBA protocols, assertion-based verification, systemverilog, code coverage analysis, Axi, formal verification, testbenches, APB, verification environments, debugging skills, AHB, digital design blocks

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

Data Analytics, static timing analysis, Statistical Modelling, Static Dynamic timing analysis, RC circuits, spice simulations, silicon correlation, Timing Concepts, CMOS devices, Physical Design, Circuit Design

Embedded C, Pcie, Perl, Verilog, Debugging, Python, Tcl, ASIC Design Flow, ONFI, systemverilog, hardware bring-up, Validation, LPDDR6, LPDDR5