Routing, Sta, CTS, floorplanning, EM, Ir, LVS, Physical Implementation, RTL-to-GDSII flow, Synthesis, Physical Design, Placement, Si, DRC

EMC EMI design techniques, High-speed PCB design principles, FPGA SoC-based architectures, DDR4 DDR5 PCIe Ethernet JESD204 SerDes, PCB stack-ups and routing constraints

Tcl, Mercurial, Svn, DDR, Git, Pcie, Perl, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, Design Verification infrastructure, System Verilog Assertions

Tcl, Verilog, C, Python, Perl, Shell, UVM methodology, systemverilog, EDA Tools

rtl development , Verilog, System Verilog, ASIC Engineer Design, Architecture exploration, Micro-architecture development

Verilog, System Verilog, FPGA tools, Synthesis, formal property verification, timing constraints development, RTL Coding, assertions, uArch, CDC checks