Usb, Fpga, Pcie, Perl, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, test bench infrastructure, FPGA and emulation platforms, AMBA, transaction level modeling, AXI4

Verilog, Oops Concepts, scripting and tool development using Perl, VCS or equivalent simulation tools, debug tools like Debussy GDB, VMM, Uvm, systemverilog

test tools automation, System Security Privacy Engineering UNECE WP29, Functional Safety Management ISO26262, C-driven, Uvm, systemverilog

Noc, C, Pcie, Perl, Python, Reset and power verification, SOC verification methodologies, SOC bring-up, Uvm, Post-silicon verification, Axi, HW FW interaction verification, Coherency verification, Bus Fabric, AHB, UPF integration

code coverage , Python, C, Debugging, Shell, Tcl, Verilog, System Verilog, Perl, Uvm, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies

Test Planning, Ovm, Debugging, CHI, Uvm, system simulation tools, AHB, UVM-based test benches, SoC design verification, APB, Axi, emulation models, AMBA protocols

Verilog, Pcie, SVA, formal verification, Assertions, Uvm, interconnect protocols, debugging complex RTL, systemverilog, CHI, AHB, Functional verification methodologies, Axi, testbench issues, Coverage