Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

simvision , Verilog, FineSim, Analog Custom Virtuoso, Xcelium, WaveView, systemverilog, debug environments, AMS verification Tools, Hspice, Cadence DiscoveryAMS, Digital Simulation Tools, Spice, PrimeSim, Synopsys XA

Verilog, Ovm, DFI protocol, LPDDR4, DDR PHY verification, Uvm, JEDEC standards, systemverilog, LPDDR5

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Design Verification, Debugging RTL Verilog designs

arm architecture , C, Ovm, Jtag, Perl, Verilog, Python, System Verilog, CPU architecture, interconnects, Uvm, power management techniques, debug architecture protocols, coherent fabrics, VHDL, SoC Verification, SVTB

Perl, Verilog, Computer Architecture, Oops Concepts, Python, VMM, UVM methodology, constrained random verification, systemverilog, functional coverage

DDR, Ethernet, System Verilog, RISC-V cores, SV coverpoints, GIC, CMN, AXI protocol, SMMU, Low-power verification, PCle, Cache and coherency verification, Uvm, UPF, ACE protocol, eMMC, CoreSight, Low-speed peripherals, ARM v8 and v7 cores, Assembly

Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency