synopsys primetime , Python Scripting, Design Compiler, SDC constraint authoring and management, Physical-aware synthesis flows, Fusion Compiler, Formality, Physical-Aware Synthesis, STA PrimeTime

Counterexample trace analysis, SystemVerilog Assertions, Constraint debugging, Formal property verification, Tcl-based formal tool flows, systemverilog, Reset and clock modeling

Perl, Bash, Python, Tcl, C, shell scripting, simulation and emulation environments, verification methodologies, Linux Unix environment, SystemVerilog UVM, test plan creation and execution

Pcie, Verilog, Ethernet, I2c, Scripting Languages, digital design principles, SOC design, ASIC development methodologies, AHB, systemverilog

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

Perl, Python, System Verilog, verification flows, formal verification, verification methodologies, coverage metrics, Profiling Tools, Uvm, constraint random verification

C, Vcs, Perl, Verilog, Python, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, ASIC Design, formal verification

Scripting skills: Tcl, boundary scan , Vcs, System Verilog, Memory BIST, primetime, Logic Equivalency checking, Post-silicon validation and debug, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, EDA Tools, BIST architectures, Tessent tool sets, TestMax