Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

Verilog, power analysis, design of SoCs, Synthesis, VHDL, Design Verification, Chisel, micro-architecture, ASIC development, systemverilog

Verilog, System Verilog, AI-powered tools, Timing Closure, EDA design processes, ASIC Design, Simulation and debugging, Functional verification tools, Synthesis tools

Scripting Languages, Perl, Tcl, Physical Verification sign-off flows and tools, PDK concepts, Physical Design implementation flow, Fusion Compiler, Foundry PDKs, ICC2, SVRF rule decks, Calibre, Innovus, ICV, Design Rules, Mixed-signal SOC environments, Backend design methodologies, Tech LEF, Custom IC design flows, Layouts, ESD reliability analysis, PERC methodologies