Cache, Soc Architecture, Verilog, power analysis, Synthesis, memory compression, FPGA design verification, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, FPGA and emulation platforms, Dft, fabric coherence, DRAM, low-power design techniques, assertion-based formal verification

System Verilog, Synthesis, microarchitecture specification, Complex Control Logic, Lint closure, Post-Silicon Debug, Timing Constraints, Networking ASICs, Designing Fabric Network On Chip, RTL coding in Verilog, Digital Design

Usb, Fpga, Soc Architecture, Pcie, Perl, Debugging, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, AMBA, formal verification, Test Bench, transaction level modeling, AXI4

Gerrit, Artifactory, Git, Jtag, Python, CloudBees, debug architecture, MBIST, CoreSight, Dft, trace scan, SoC debug ecosystems, ELA telemetry frameworks, on-chip debug architectures, IJTAG