Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

Tcl, Python, PERL, Physical Verification, SNPS CAD Flow, SNPS CDNS-based tools, RTL-GDS flows, Sta

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols

Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

monte carlo , python, AI ML, Cadence Virtuoso, Spice Simulator

Perl, Verilog, Python, Arm CoreSight IP, power clock domain crossing, reset domain crossing, ARM-based designs, systemverilog