Perl, Verilog, Python, Arm CoreSight IP, power clock domain crossing, reset domain crossing, ARM-based designs, systemverilog

C, Numpy, Ethernet, Matlab, Mentor Veloce, LPDDR, high-speed Serdes, Cadence Palladium, FPGA designs, Synopsys Zebu, FPGAs, DSP designs, MIPI, post-silicon bring-up, signal processing functionality, pre-silicon validation, System Verilog RTL Code, ASICs, AMBA protocols, Diagnostics Firmware development

C, Perl, Verilog, Shell scripting, Python, Tcl, SVA, UVM assertions, systemverilog

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

Tcl, Shell scripting, Python, Perl, Debugging, Uvm, systemverilog, Mixed-Signal Verification