C, Numpy, Ethernet, Matlab, System Verilog, Mentor Veloce, Cadence Palladium, pre-silicon validation, FPGA designs, AMBA protocols, high-speed Serdes, Rtl Design, MIPI, DSP designs, Diagnostics Firmware development, Synopsys Zebu, LPDDR

C, Pcie, Ethernet, SV, CXL, UCIe, Uvm, systemverilog

C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator

Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP

Ovm, Spi, Soc Architecture, Verilog, I2c, System Verilog, Python, Usb, Perl, Ethernet, Arm, Tcl, Bus Matrix design, MIPS, DFT concepts, Uvm, Rtl Design, Synthesis, RDC, Power estimations, Timing constraint SDC, ASIC design flow, LINT, Formal CDC, MBIST, Axi, AMBA, BUS Protocols, Low-power design, Timing Analysis, peripheral IPs

Schematic design, MATLAB, Python, Synopsys Custom Compiler, BERTs, Spectre, Hspice, Cadence Virtuoso, Layout interaction, behavioral modeling, Lab measurements, BER estimation, High-speed oscilloscopes, Post-layout verification, Design sign-off, Jitter budgeting, Parasitic Extraction, Silicon bring-up

PERL, Python, Tcl, Synthesis, Formal Equivalence, DRC, Ir, LVS, EM Signoff