Spi, Verilog, I2c, System Verilog, OTP MTP Efuse read writes controller design, Sta, Root Cause Analysis, Power product design, Post layout verification, Register read write Trimming of Analog parts functions, PMBUS, Placement and Route, Synthesis, Power Estimation, Verification test case development, Power Chip Communication I Ps, DFT strategy and implementation, Silicon debugs, Data bus handling, Digital Design, Clock Domain Crossing, Feature extraction, Verification test planning, Logic Synthesis, formal verification, Timing Analysis

Verilog, System Verilog, Digital Logic Design, Synthesis, Pre-Silicon Verification, Post-Silicon Support

code coverage , C, Shell, Perl, Verilog, Debugging, Python, System Verilog, Tcl, UVM methodology, Metric Driven Verification, formal verification methodologies, assertions, constrained random methodologies, functional coverage

Perl, Python, Sequencers, Agents, Checkers, Uvm, Functional coverage, systemverilog, Assertions, Coverage models, Verilog-AMS, Verification methodology, Scoreboards, Monitors, Constrained random techniques, Verilog-A

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation

static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts