simvision , python, perl, Hspice, Xcellium, Finseim, Agentic AI Flow, vsim, virtuoso, digital mixed signal circuits, Waveview, SV UVM based Verification, Digital Mixed signal Verification

Makefile, Windows, Perl, Linux, Python, IP level ASIC verification, SystemVerilog language, UVM testbenches, automating workflows in a distributed compute environment, acceleration, formal verification, UVM concepts, simulation profile efficiency improvement, debugging RTL code using simulation tools, using AI tools, testbenches processes and flows

Makefile, Windows, Shell, Linux, Perl, Python, AI tools, IP level ASIC verification, SystemVerilog language, UVM testbenches, automating workflows in a distributed compute environment, acceleration, formal verification, UVM concepts, simulation profile efficiency improvement, debugging RTL code using simulation tools, testbenches processes and flows

Makefile, Windows, Linux, Perl, Python, IP level ASIC verification, AI tools, SystemVerilog language, UVM testbenches, automating workflows in a distributed compute environment, acceleration, formal verification, UVM concepts, simulation profile efficiency improvement, debugging RTL code using simulation tools, testbenches processes and flows