Perl, Python, System Verilog, Uvm, analog mixed-signal AMS, formal verification, VHDL, digital mixed-signal simulations

Coverage models, CPU Core Verification, Constrained-random tests, Scoreboards, Checkers, Architecture Validation, Uvm, systemverilog, Testbenches

System Verilog, Finesim, HSIM, Test Bench development, XA hspice, Uvm