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DFT Lead - ATPG

AMD Ventures
Bengaluru, India

Skills:

Perl, Shell scripting, Scan Insertion, IEEE1500, Gate-level simulation, Test cost reduction analysis, VCS simulation tool, DFT architecture, Synopsys Tetramax, Scan memory BIST, Verilog RTL design, JTAG 1149.x, ATPG pattern generation, Design for Test methodologies, Post silicon support, Mentor testkompress

Early Applicant

DFT Lead - ATPG

Inotec AMD
Bengaluru, India

Skills:

Perl, Shell scripting, DFT verification, VCS simulation tool, Synopsys Tetramax DFTMAX, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Mentor testkompress, Design for Test methodologies

Early Applicant

DFT Lead - ATPG

AMD Telecom
Bengaluru, India

Skills:

Perl, Shell scripting, DFT verification, VCS simulation tool, Synopsys Tetramax DFTMAX, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Mentor testkompress, Design for Test methodologies

Early Applicant

DFT Lead - ATPG

AMD Maquinaria
Bengaluru, India

Skills:

Perl, Shell scripting, DFT verification, VCS simulation tool, IEEE1500, Synopsys Tetramax, Scan memory BIST, Verilog RTL design, JTAG 1149.x, Design for Test methodologies, Mentor testkompress

Early Applicant

Senior / Lead DFT Solutions Engineer Chip Methodology & Automation (CMA)

Arm
Bengaluru, India

Skills:

Shell, Jtag, Python, Tcl, scan compression, IEEE 1149.x, MBIST, DFT implementation methodology, DFT EDA tools, IEEE 1687, ATPG, hierarchical DFT methodologies, LBIST, automation and scripting skills

Early Applicant

DFT Engineer - Sr. / Lead

ALTEN Calsoft Labs
Bengaluru, India

Skills:

Tcl Scripting, Perl, Dft, Gate level simulations, Zero delay Timing Delay simulations, PD flow knowledge, ATPG Pattern generation, Timing Formal verification, JTAG P1500 protocols, SCAN DRC

Early Applicant
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