Usb, Vcs, DDR, Pcie, Perl, Ethernet, Shell scripting, Python, Tcl, Xcelium, Uvm, systemverilog, Questa

Usb, Jtag, Pcie, Perl, Ethernet, Python, System Verilog, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB

System Verilog, Ovm, Debug, Validation Verification, Uvm, verification architecture, Emulation, validation test suites, coverage closure, test plan execution, Silicon Design, constrained random verification methodologies

System Verilog, Python, Tcl Scripting, UVM methodology, gate-level simulation, debug skills, DV sign-off flows, SoC TB architecture, RTL integration, HW–SW interaction, test-plan creation, power-aware verification, UPF-based methodologies

Debugging, Mixed-Signal Verification, Uvm, systemverilog