code coverage , Regression Analysis, Test Plan Creation, formal verification, SV assertions, Uvm, coverage-driven verification, systemverilog, functional coverage

arm architecture , C, Ovm, Jtag, Perl, Verilog, System Verilog, Python, CPU architecture, interconnects, Uvm, debug architecture protocols, power management techniques, coherent fabrics, VHDL, SoC Verification, SVTB

Low Power Verification., C Programming, SoC Verification, systemverilog, Uvm, ARM SoC, Gate Level Simulation, Coverage Closure, APB, AHB, Axi

Perforce, Vcs, Git, Shell, Perl, Python, Tcl, SoC ASIC Verification, Xcelium, Functional coverage assertions, Uvm, systemverilog, Full Chip Verification, Constrained random verification, Questa, SVA

Perl, Verilog, Python, advanced verification methodologies like e-specman SV-UVM, debug tools like Indago GDB, SV scripting languages, Cadence or equivalent simulation tools

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Python, Pcie, Perl, Shell, DDR, MIPI, Uvm, JESD204B, UPF, systemverilog, USB3, Dft

CPU GPU benchmark characterization, SOC design verification, mobile SOC performance model development, Linux drivers, runtime, workload characterization, performance analysis tools, systemverilog, Performance Analysis