C, Verilog, Scripting, RTL testbench debug, interconnects, Arm-based SoC architecture, memory hierarchy, Uvm, UPF, systemverilog, coverage closure, coherency

Usb, Vcs, DDR, Perl, Pcie, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog, CXL, LPDDR, high-speed protocols

arm architecture , C, Ovm, Jtag, Perl, Verilog, Python, System Verilog, CPU architecture, interconnects, Uvm, power management techniques, debug architecture protocols, coherent fabrics, VHDL, SoC Verification, SVTB

C, Shell, Perl, Verilog, System Verilog, Python, Cadence Tools, Xcelium, Uvm, safety simulator, VHDL, vManager, Formal applications

DDR, Shell, Pcie, Perl, Python, JESD204B, Uvm, UPF, GLS, systemverilog, MIPI, Dft, USB3

Perl, Python, SV, low power simulations, Uvm, testbench development, debugging gate level simulations, assertions coding

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB