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Showing 4 jobs
Skills:
System Verilog, JTAG protocols, ATPG, Logic Equivalency checking, Post-silicon validation and debug
Skills:
boundary scan , System Verilog, ATE patterns, Memory BIST, JTAG protocols, ATPG, Logic Equivalency checking, Post-silicon validation and debug, BIST architectures, P1687, Gate level simulation debugging
Skills:
boundary scan , Vcs, Perl, System Verilog, Python, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax
Skills:
Dft, Design For Testability, Scan Insertion, Scan Compression, DFT Compiler
