C, DDR, Pcie, Memory Consistency Models, verification components, Clock and Power Controllers, Caches, Coherency, Uvm, Security, systemverilog, Packet Processors, Hierarchies, standard verification methodology, LPDDR, Interconnect Protocols

Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Verilog, Computer Architecture, advanced stimulus generation, Uvm, coverage-driven verification, systemverilog

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, AMBA, linting, AHB

random testing , Oops, Fpga, Pcie, Verilog, System Verilog, coverage assertions, Debug, Ethernet based protocols, VCS simulation flow, Otn, Uvm, VMM, AXI memory controllers, adversarial testing