Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Perl, Python, Tcl, Sta, Physical Design, ASIC Implementation, EM, Ir, PDN, make

Ecos, Perl, Python, Tcl, FC PrimeTime, Sta, Design Compiler, CTS, EM, physical signoff, Ir, advanced-node SoCs, congestion optimization, ASIC Physical Design Full-Chip Implementation, MCMM, design closure, low-power implementation, PPA trade-offs, Synopsys ICC2

power integrity , Perl, Python, Tcl, FinFET process technologies, Ansys RedHawk-SC, Quantus PrimePower, Cadence Voltus, physical-design implementation, Joules, EMIR analysis, StarRC, current and activity models

Physical design implementation, Synthesis, Signoff implementation tools, PPA optimization, Scripting skills, RTL to GDS implementation