power analysis, 3D IC design, Physical Design flow, IR Signoff Tools, Ansys tools, PTPX, Low power implementation techniques

Logical and physical optimization, PDN analysis, CTS, power analysis, DFM and Physical verification, Physical Design, Timing Closure, ASIC Implementation, Synthesis, Floor Planning, Structured clock tree, Place And Route, STA and Timing closure

control logic , Storage Devices, Embedded Firmware, C, Data movement, Rtos, Jtag, Performance Tuning, Hardware interfaces, Reliability engineering, state machines, Error detection, Device initialization

congestion management , Tcl, Python, Perl, Synopsys ICC2, Cadence Innovus, clock gating, clocking methodologies, primetime, physical implementation, power-aware physical implementation, clock domain partitioning, SoC-level floorplanning, clock tree architecture, Timing Closure, low-power design techniques

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

statistical data analysis , System integration, Firmware, Fluidics, Analytical Scientific Instrumentation, Electronics, Resource sharing, Hardware synchronization, Dynamic time allocation, Jmp, Risk Analysis, Excel statistics macros, System-level control logic architecture, Minitab, Software, Life Sciences, Embedded computers, medical diagnostics

Assembly Language, Rtos, Github, C, Unit Testing, Gdb, Zephyr, Spi, Jtag, Freertos, System Testing, Version Control Systems, Microprocessors, Gitlab, I2c, Python, Zigbee, Pwm, Uart, Git, Integration Testing, Bitbucket, Ble, Oscilloscopes, bare metal programming, Microcontrollers, FPGAs, debug tools, low level drivers, Logic Analysers

Perl Scripting, Tcl, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, High Frequency Design, Power Gating, PDN Methodology, PPA Targets, Timing Signoff

statistical data analysis , System integration, Firmware, Fluidics, Analytical Scientific Instrumentation, Electronics, Optical hardware, Dynamic time allocation, Hardware synchronization, Resource sharing, Jmp, Risk Analysis, Excel statistics macros, System-level control logic architecture, Minitab, Software, Life Sciences, Embedded computers, medical diagnostics