power integrity , Routing, Perl, Python, Tcl, Physical Sign off, Chip finishing, Metal fill, Tapeout checks, Clock Trees, Physical Verification, Sealring, Signal Integrity, RTL2GDS flow, Floorplans, Power Distribution Network, Physical Design, Placement, Timing Closure, Equivalence Check, Synthesis Constraints

Java, C, Python, SIMD vectorization, Cache-aware execution, Performance profiling, Parallel execution strategies, qemu, Benchmarking, Optimization

Perl, Python, Tcl, Skill, Calibre PVS, Cadence Virtuoso, High-voltage process technologies, IR drop, Physical verification tools, PEX, Reliability-aware layout, Antenna density, High-current routing, Layout methodology improvements, LVS, Parasitic control, Latch-up prevention, Electromigration, Noise isolation, Thermal effects, ERC, DRC, Extraction and reliability tools, Tape-out readiness, Guard rings

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

monte carlo , python, AI ML, Cadence Virtuoso, Spice Simulator