Perl, Python, Tcl, Assertions SVA, Constrained-random verification, Uvm, Functional coverage, systemverilog

Perl, Python, Tcl, Assertions SVA, high-speed PHY IPs, verification automation frameworks, Uvm, Functional coverage, systemverilog, CI CD verification flows, Constrained-random verification, AI-assisted verification productivity

C, Usb, Makefile, Windows, Shell, Linux, Perl, Pcie, Verilog, Ethernet, Ruby, System Verilog, Systemc, IP level ASIC verification, HLS tools, Graphics pipeline knowledge, UVM testbenches, automating workflows in a distributed compute environment, AXI ACE Protocols, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, TLM

C, Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

Jasper, Pcie, Verilog, System Verilog, Synopsys VC-Formal Magellan, formal property checking tools, Uvm, Cadence IEV, Synopsys VCS, Cadence IES, HBM, DDR4, AXI3, SVA