Usb, Verilog, Arm, System Verilog, Ethernet, Pcie, DDR, linting, LPDDR, Synthesis, IO mixed signal designs, gearing logic, mmc, high speed serial interfaces, ip development, Axi, RiscV, cdc, AMBA, Rtl Design, Sta, micro-architecture, Sd, unit level verification, Network On Chip Bus Interconnect

Asterisk architecture, Linux-based systems, system and appliance security practices, VoIP systems, SIP trunk setup, Asterisk telephony platforms, multi-site connectivity

Logic Design, System Verilog, Armv7-A processor architecture, Micro-Architecture Design, Axi, Synthesis, Cortex A9, VHDL, APB, Equivalence checking, RTL Coding, Cortex A7, AHB, Lint and CDC, Digital Design

simics , Software Architecture, Computer Architecture, Python, System C, gem5, qemu, RISC-V architecture, Virtualizer

Machine Learning, Computer Architecture, Algorithms, Opengl, Directx, Computer Graphics, Automation Systems, AI Agents, Operating System Fundamentals

Verilog, Asynchronous interface, Synthesis, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Multi Clock designs, System-Verilog, formal verification

React, Gcp, System Design, Node.js, Rest Apis, Azure, AWS, microservices architecture

Typescript, Javascript, Automation Frameworks, Api Testing, Playwright, GraphQL APIs, CI CD pipelines, GitHub workflows

threat modeling , API security, Owasp Top 10, Data protection and privacy concepts, Secure SDLC practices, AI ML security risks, Secure system design, Architecture and design-level security reviews, DevSecOps tooling, Application security principles, Authentication and authorization mechanisms

Performance Testing, Test automation, Python Programming, Distributed systems validation, Linux systems knowledge, Git workflows