power system studies , cdegs , Insulation Coordination, Harmonic Studies, Cable Ampacity, Earthing Design, Relay Settings, Arch Flash Studies, PSCAD, Relay Coordination, Power Factory, Grid Connection related PSSE, Unbalance Load Study, Short Circuit Studies, Australian Standards, Motor Starting Studies, DigSilent, Etap

Embedded C, Fpga, Dac, Uart, Spi, Gpio, Debugging Tools, Usart, I2c, Flash, Python, Timers, ADC, Ethernet based protocols, Modbus, DMA

Test Automation, Embedded Software Development, Python, Hardware design support, Subject matter expertise, Failure root-cause analysis, Alternative part qualification for power electronics boards, Documentation and scientific rigor, Product Validation, Technical mentoring, Field quality improvement, Bench testing, PCB layout and simulation tools, Cost reduction through VAVE

Fpga, C, Embedded Linux, Git, Python, digital control systems, Signal Processing, Communication Protocols, electrical codes, UPS designs, Safety Standards, VHDL, Embedded Systems, tool chains

Tcl Scripting, Verilog, Rtl Design, FPGA hardware platforms, VHDL, FPGA development, Questasim, Timing Analysis

bandgap references , power converters , Design extraction and simulation flows, Analog layouts, Source-Sink LDOs, Voltage Regulators, High speed level shifters, Current Sense SAR ADCs, FET layouts, Analog Circuit Design, Temperature Sensor, Power Management ICs, Switch Cap circuits, Ultra-low power Oscillators, Comparators, Control Loops, Op-Amps, Noise isolation techniques, Analog Buffers, Thermal Under-Voltage Over-Voltage Over Current, Charge Pumps

Spi, Uart, Dac, Usart, Debugging Tools, Embedded C, I2c, Gpio, Timers, Python, Flash, Industrial Automation, FPGA related developments, VFD technologies, Modbus, Ethernet based protocols, ADC, DMA, MCU peripherals

Intel/ Altera development tool chains, FPGA Design, cdc, Reverse Engineering, test bench for verification, RTL design using VHDL/verilog, Design of IP cores-protocols-HDLC-SPI, STA and other timing considerations