power optimization , layout verification , static timing analysis, routing, Verilog, Perl, Python, Tcl, Synthesis, submicron process node technologies, power delivery methodologies, Power Estimation, formal verification, VHDL, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis, DRC, LVS

Cpu, Gpu, physical design engineering, ASIC RTL2GDS implementation, high performance design schema, power optimization techniques, Electrical Engineering, Computer Science