Perl, Verilog, Python, Tcl, Timing Analysis, Digital Design, system debug, FPGA architecture, System C, Vivado toolchain, Rtl Design, high-speed connectivity protocols, VHDL, Microarchitecture, AMD Xilinx FPGA

Perl, Verilog, Python, Tcl, microarchitecture development, Timing Analysis, Digital Design, system debug, static timing flows, FPGA architecture, System C, Vivado toolchain, Rtl Design, high-speed connectivity protocols, CDC synthesis flow, formal checking, VHDL, LINT, AMD Xilinx FPGA

Perl, Verilog, Python, Tcl, Timing Analysis, system debug, FPGA architecture, Vivado toolchain, Rtl Design, System C, high-speed connectivity protocols, VHDL, AMD Xilinx FPGA