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RTL Design Engineer FPGA High-Speed Connectivity IP

AMD Telecom
Hyderabad, India

Skills:

Perl, Verilog, Python, Tcl, microarchitecture development, Timing Analysis, Digital Design, system debug, static timing flows, FPGA architecture, System C, Vivado toolchain, Rtl Design, high-speed connectivity protocols, CDC synthesis flow, formal checking, VHDL, LINT, AMD Xilinx FPGA

Early Applicant

RTL Design Engineer FPGA High-Speed Connectivity IP

AMD Maquinaria
Hyderabad, India

Skills:

Perl, Verilog, Python, Tcl, Timing Analysis, system debug, FPGA architecture, Vivado toolchain, Rtl Design, System C, high-speed connectivity protocols, VHDL, AMD Xilinx FPGA

Early Applicant
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