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Showing 3 jobs
Skills:
perl scripting, Jasper, Verilog, Computer Architecture, System Verilog, VSI-FV, digital systems, assembly x86 code, IEV, IFV, CPU verification, Formal Verification methodology
Skills:
perl scripting, Jasper, Verilog, System Verilog, digital systems, assembly x86 code, VSI-FV, IEV, IFV, CPU verification, Formal Verification methodology
Skills:
Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower
