Low-power Implementation, Physical Verification, Physical Design, Timing Closure, Floor Planning, EDA Tools, Power Grid Design, Power Planning

bandgaps, capacitor matching, CMOS image sensors, Simulation, Cadence, noise analysis, Pll, Dft, bias op-amps, transistor level circuit design, top chip integration, Verification, LDOs, tapeout, AI tools, ADC architectures, analog mixed signal design, SERDES, switched-cap circuits, Timing Analysis, Silicon Bring up, feedback and compensation techniques, TCAD, high-speed TX, CMOS pixel design techniques

static timing analysis, VHDL, clocking resets, Timing Analysis, verification methodologies, EDA tools for synthesis, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC, RTL design using Verilog, low-power design techniques, Simulation

Logic Design, Static Timing Analysis, Tcl, Python, Perl, Jasper, IR drop, coverage analysis, RTL lint tools, ATE debug, Logic Synthesis, EDA Tools, Sta, RTL2GDS flow, Logic Equivalent Checking, Cadence Modus, Synthesis, post silicon validation, Verification, DFT concepts, ATPG tools, RTL implementation, debugging skills, Scan Insertion