C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

Perl, Python, constraint-random testing, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

Asic verification, digital design verification, Uvm, test bench architecture, systemverilog, GIT version control, C Language

Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP