Automation scripts, formal verification, Gate Level Netlist, Power Estimation, RTL Lint, RTL DFT Analysis, Logic Physical Synthesis

Verilog, Timing analysis closure, Power analysis optimization, RTL Coding, CPU Core RTL Design, systemverilog

Verilog, Python, bus architectures, Synopsys, performance modeling tools, Cadence Tools, accelerators, memory hierarchies, low-power design techniques, arithmetic units

Verilog, Logic Design, Physical Design, Timing Constraints, RTL constraints, LINT, Vlsi, timing exceptions, System-Verilog, cdc

rtl development , power delivery , Verilog, ASIC design flow, Dft, mixed-signal chips, Behavioral Circuit Modeling, Timing Analysis, Custom Digital Design, power management solutions, System-Verilog

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

rtl development , Jtag, Verilog, I2c, ASIC design flow, Timing Analysis, System-Verilog, mixed-signal chips, SPMI, Custom Digital Design, Behavioral Circuit Modeling, Dft, power management solutions

Verilog, Python, Tcl, Synthesis, RTL lint and CDC checks, FSM design and implementation, LEC, UPF, systemverilog, Reset synchronization, Rtl Design