architecture-level validation, DFT concepts, SoC Design Verification, MBIST, UVM testbench development, systemverilog, ATE functional patterns, reset boot flows, x86 processor-based SoC IP DV, Scan, DV sign-off, post-silicon debug, SerDes loopback IO validation, functional coverage

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage

layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, design rules, Vlsi Design