Verilog, System Verilog, Axi, APB, AMBA protocols, low-power design techniques, AHB, simulation and debugging tools, ASIC SoC design environments, synthesis timing closure

Test Planning, C, Systemc, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, formal verification, constrained-random verification, power-aware verification