Silicon Validation, PERL, Debugging, Python, analog simulation, noise analysis, Analog Circuit Design, stability and compensation, CMOS technology, silicon bring-up, virtuoso, device mismatch and variation

UVM Test Bench development, power simulation on VCS, script writing in Python, UPF

Perl, Python, RTL debug skills, SV – UVM Assertions based verification, ARM based system architecture, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi

code coverage , System Verilog, Asic verification, Gate level simulations, IP level verification, UVM Verilog, testbench architecture development, testbench component developments, functional coverage

Verilog, testbench creation, RTL debugging, logic simulation, AMS simulations, Uvm, score boarding, systemverilog, Verilog-A, DFI protocols, code coverage analysis

MATLAB, Python, mechanical analysis, Cadence Clarity, Pads, Hspice, IC package layout tools, PowerSI, channel simulations, 3D package development, SI-Wave, high speed signaling, SIwave, Spectre, microwave theory, Ads, scripting tools, APD, 3-D EM simulation tools, Ansys HFSS, packaging technologies, EM transmission lines, circuit design tools

Logic Design, Gate-level simulations, Static-timing closure, Custom SoC ASIC products, formal verification, Synthesis, Debug skills, Block-level function verification, Front-end design tools and methodologies, Micro-architecture, Rtl Design