Tcp, Pcie, Ethernet, System Verilog, RDMA, Palladium, Test benches, Zebu, Veloce, ASIC verification using UVM, HAPS, Data path verification, formal verification

architecture-level validation, DFT concepts, SoC Design Verification, MBIST, UVM testbench development, systemverilog, ATE functional patterns, reset boot flows, x86 processor-based SoC IP DV, Scan, DV sign-off, post-silicon debug, SerDes loopback IO validation, functional coverage

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage

Tcp, Pcie, Ethernet, System Verilog, RDMA, Data path verification performance tests, Building test benches, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

System Verilog, Tcp, Ethernet, Pcie, formal verification, Data path verification performance tests, Building test benches, RDMA, Zebu, HAPS, ASIC verification using UVM, Palladium, Veloce