System Verilog, Building test benches from scratch, ASIC verification using UVM

Usb, Fpga, Pcie, Perl, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, test bench infrastructure, FPGA and emulation platforms, AMBA, transaction level modeling, AXI4

Tcp, System Verilog, Ethernet, Pcie, formal verification, Forwarding logic Parsers P4, Building test benches from scratch, RDMA, Zebu, System Verilog constraints structures and classes, HAPS, ASIC verification using UVM, Verifying sophisticated blocks clusters and top level for ASIC, Palladium, Veloce

System Verilog, Tcp, Ethernet, Pcie, formal verification, Data path verification performance tests, Building test benches, RDMA, Zebu, HAPS, ASIC verification using UVM, Palladium, Veloce

Tcp, Pcie, Ethernet, System Verilog, RDMA, Data path verification performance tests, Building test benches from scratch, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification