System Verilog, Tcp, Pcie, Ethernet, Building test benches from scratch, ASIC verification using UVM, Gate Level Simulations, Forwarding logic Parsers P4, RDMA, Zebu, Veloce, Palladium, HAPS, formal verification

Tcp, Pcie, Ethernet, System Verilog, Building test benches from scratch, Gate Level Simulations, Forwarding logic Parsers P4, RDMA, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Verilog, power analysis, design of SoCs, Synthesis, VHDL, Design Verification, Chisel, micro-architecture, ASIC development, systemverilog

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

display technologies , Python Programming, Functionality, Bit Depth Color, OS Ecosystems, Bitstream Verification, MIPI DSI-2, Introspect SV series systems, FPGA platforms, Scaling Processing, PVT Testing, Frame Buffer, Lab Instrumentation, Pixel Formats, SV UVM, Low-Level Software, Continuous Integration tools

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage