Jtag, Perl, Python, Tcl, scan-chain based logical tests, DFD, Skill, MBIST, Dfm, Dft, ATPG, CAD layout tools, Scan Compression, Tessent based tools, silicon diagnostics

Vcs, Verilog, Scripting Languages, Debug, verification methodologies, Simulation, Uvm, coverage infrastructure tools, VHDL, stimulus checking, NC, Verilator

Linux, Gdb, Python, Device Drivers, Clock management, Layer 1 and Layer 2 networking technologies, Timing synchronization

bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation

Gerrit, Artifactory, Git, Jtag, Python, CloudBees, debug architecture, MBIST, CoreSight, Dft, trace scan, SoC debug ecosystems, ELA telemetry frameworks, on-chip debug architectures, IJTAG

Debugging, UVM C verification methodology, Asic verification, Pre-Silicon SoC verification, Post-Silicon validation