Soc Architecture, System Verilog, scoreboarding, digital design fundamentals, verification concepts, simulation logs, Uvm, ASIC SoC functional verification, waveform tools, constrained-random stimulus, BUS Protocols, assertions, SVA, functional coverage

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

shell scripting, Perl, Python, Tcl, mixed-signal design verification, Cadence Spectre simulation, Cadence Mixed-Signal Design Environment, SV UVM-based testbenches, VerilogAMS, behavioral modeling, systemverilog

Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

DDR, Ethernet, System Verilog, RISC-V cores, SV coverpoints, GIC, CMN, AXI protocol, SMMU, Low-power verification, PCle, Cache and coherency verification, Uvm, UPF, ACE protocol, eMMC, CoreSight, Low-speed peripherals, ARM v8 and v7 cores, Assembly

Pcie, Regression Testing, Verilog, Ethernet, assertions, Uvm, systemverilog, functional coverage, constrained-random verification

Design Verification, ASIC Design, Verification Planning, systemverilog, Rtl Design