routing, Sta, CTS, ASIC PD methodologies, digital design fundamentals, Extraction, Floor Planning, PNR, Placement, EM IR closure, signoff

power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies

Pcie, DDR, C, Soc Architecture, Scripting Languages, Python, Emulation, hardware software integration, RTL design verification, Power Characterization

synopsys tools , Scripting, Soc Architecture, Physical Design, design validation, Microarchitecture, Design Principles

power optimization , routing, Perl, Python, Tcl, physical design flows, floorplanning, digital VLSI concepts, IR-drop, Timing Analysis, Tempus, voltus, Cadence Innovus, LVS, EM analysis, Physical Verification, Rtl Design, EDA Tools, DRC, Placement

Soc, Pvs, Tcl, Designing

Design Verification, ASIC Design, Verification Planning, systemverilog, Rtl Design

Design Planning, Architecture and Microarchitecture, ASIC designs, Rtl Design, Physical Design Support, Synthesis and Optimization