hardware engineering , automation, physical design methodologies, lower technology nodes, power gating, sign-off optimizations, multi-voltage domains, deep sub-micron technology, Netlist2GDS, ASIC design flows, Floorplan, Circuit Design, device physics

routing, Shell scripting, Static Timing Analysis, Python, Perl, Ddr3, Tcl, Sta, IR drop, OCV, CTS, LVS, LPDDR PHY hardening, ECO implementation, antenna checks, MMMC, POCV, floorplanning, EM analysis, CRPR, Physical Verification, Signal Integrity, crosstalk, DRC, Timing Closure, Placement, ASIC Physical Design flow, DDR5, DDR4, AOCV

redhawk , Tcl, Perl, VSLP, Synthesis, ICC, Logic equivalence checking, Low Power checking, Calibre, Power signal integrity, Physical Design Verification, SDC clean up, Place And Route, DRC, Physical Design, SOC design, Mixed signal block integration, Dc, Timing Closure, LVS, Pt, STA timing, Deep sub-micron designs, Formality, Manufacturability

Pcie, C, Python, Scripting Languages, DDR, Soc Architecture, hardware software integration, Power Characterization, Emulation, RTL design verification

routing, physical design flows, digital VLSI concepts, Tempus, floor-planning, Cadence Innovus, Voltus, Timing Closure, EDA Tools, Placement, Logic Synthesis, Rtl Design

static timing analysis, Python, Asic Physical Design, place-and-route Encounter Innovus ICC, high-speed SerDes, physical verification DRC LVS, 3DIC implementation methodologies, DFT methodologies, Verilog RTL, Cadence Virtuoso, Genus Design Compiler, RTL Compiler, Clock Tree Synthesis, scripting or programming languages, ASIC synthesis