C, Gnu, Python, System Verilog, Systemc, TLM 2.0, Tasking, PLS Lauterbach, CCI, Uvm, VLAB, T32, Synopsys Virtualizer, ASTC

C, Usb, Uart, Bash, Spi, Perl, Pcie, Verilog, I2c, Test Plan Creation, System Verilog, Python, Tcl, gate-level simulations, i2s, Uvm, coverage driven verification methodology, DP, Sd, Test Development, test-bench development, Gate Level Power-Aware simulations, test coverage assessment

test writing , System Verilog, object-oriented programming, UVM methodology, test plan implementation

Verilog, testbench creation, RTL debugging, logic simulation, AMS simulations, Uvm, score boarding, systemverilog, Verilog-A, DFI protocols, code coverage analysis

Cryptography, Verilog, VCS tools, JasperGold, Uvm, code coverage methodologies, systemverilog, Axi, APB, RSA algorithms, SiFive RISC processors, PRNG, VC Formal, VCF, AHB