C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

Tcl Scripting, Ovm, Unix Shell Scripting, DDR, Pcie, Perl, Verilog, Debugging, System Verilog, test bench development, CMOS logic design, IC chip design development flow process, CMOS device operation and characteristics, Simulation, verification plans, Uvm, Circuit Analysis, CAE CAD tools, Axi, VHDL, AHB, Circuit Design, coverage assertion driven verification

Python, Tcl, Power-domain planning, Design validation, DRC LVS EM IR, Parasitic modeling, Global routing, Skill, Top-level virtual flat placement, AI flows, APR flow, Timing budgets, Block shaping, Memory Logic Analog circuits, Modeling and simulation

C, Sql, Python, HTML, Scripting Languages

rtl development , Ethernet, Pcie, Usb, Vlsi, Verification, UFS, Physical Design, Digital Design, Timing, micro-architecture