Technical Documentation, Autocad, Inverter selection, Energy modelling, Costing Sheet, Calculations, Grid interconnection requirements, DC AC cable sizing, Performance Analysis, Interconnection applications, System layout design, Bom, Open access regulations, Engineering Drawings, Electrical Engineering, code compliance, Shading analysis tools, Solar PV system design, Mms, String sizing, Pvsyst, Single-line diagrams, Site assessments, Permitting approvals

Ms Office Suite, Transmission line modelling, Microstation, Knowledge of BS IEC IS IEEE ANSI standards, PLS-Pole, PLS-CADD, Autocad, PLS-Tower

Design for Manufacturing (DFM), Design for Assembly (DFA), PDM 3D com, Welded structures, Railway standards EN DIN UIC IRS, Catia V5, Bogie systems and structural load paths, GD T tolerance stack-up, Manufacturing processes welding machining assembly, PLM ENOVIA

Dfs, DFA, PMI models Drawings MBD, Engineering Bill of Material creation update and modification, Sheet Metal components Models Drawings, PMI environment, Industry codes and standards such as ASME Y14.5, Fabrication Models Drawings, CAD modelling detailing, Dfm, Manufacturing drawings creation and drawing reading

british standards , Microsoft 365, UK EU project experience, Revit modelling coordination, Autocad, Technical schematics capability, Technical layout capability and spatial coordination, General ventilation system calculations and design, Smoke ventilation system calculations and design, Thermal fluid distribution system calculations and design, BS 9991, CIBSE codes and guidance, BS 9999, BS EN 1366

bom creation , detailing assembly, Catia V5, Airbus methodologies and processes

Matlab, Worst case identification, Monte Carlo analysis, Physical layout management, AMs, Analog Circuit Design, Spectre, Cadence tool set, Top level simulation, Simplis, Post layout parasitic extraction, Schematic generation and simulation, Top level verification, Knowledge of device physics and process technologies, Block level modelling, Simulation data analysis, IC transistor level implementation, IC system partitioning and architectural tradeoff analysis, Power IC design, Signal grounding and routing tradeoffs, Die area optimization