System Verilog, Finesim, HSIM, Test Bench development, XA hspice, Uvm

System Verilog, TLBs, Store buffer, Memory consistency models, Speculative loads, Physical register files, Flush replay, Debug tools, MMU, Cache hierarchy, Instruction fetch, Page table walkers, Interrupt handling, Register mapping, Protection, Uvm, LR SC, Reorder buffer, Bypass networks, Scheduler, Stores, Atomics, Coherence protocols, Decode rename, Issue queue