redhawk , power integrity , Debugging, Tcl, Perl scripting, power network planning, low-power design methodologies, reliability EM IR analysis, place-and-route, VLSI logic design, system-level floorplanning, Calibre, Innovus, Timing Closure, Clock Tree Synthesis

Tcl, Verilog, Python, Perl, Clock Tree Synthesis, object-oriented programming, Place And Route, EDA Tools, floorplanning, VHDL, RTL-to-GDSII implementation, Synthesis, Timing Closure

Verilog, Computer Architecture, Subsystem hardening, Synthesis, object-oriented programming, floorplanning, Place And Route, DFT insertion, digital logic, VHDL, RTL-to-GDSII implementation, EDA Tools, Timing Closure, Clock Tree Synthesis

routing, Signal Integrity, CTS, floorplanning, Timing Closure, IR EM and variability analysis, Placement, low-power design, ASIC SOC physical design implementation, Physical Verification

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis