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Showing 5 jobs
Skills:
Perl, Python, Tcl, Assertions SVA, Constrained-random verification, Uvm, Functional coverage, systemverilog
Skills:
Jasper, Verilog, System Verilog, Cadence IEV, Synopsys VCS, Synopsys VC-Formal Magellan, Cadence IES, Formal property checking tools, Uvm, Simulation Tools
Skills:
Verilog, System Verilog, SVA, Synopsys VCS, assertion and coverage-driven verification, Uvm, formal property checking tools, Cadence IES
Skills:
Jasper, Pcie, Verilog, System Verilog, Synopsys VC-Formal Magellan, formal property checking tools, Uvm, Cadence IEV, Synopsys VCS, HBM, Cadence IES, SVA
Skills:
Verilog, System Verilog, assertion and coverage-driven verification, Synopsys VCS, Cadence IES, formal property checking tools, Uvm, SVA
