Perl, Python, System Verilog, verification flows, formal verification, verification methodologies, coverage metrics, Profiling Tools, Uvm, constraint random verification

Perl, Python, Tcl, Pcie, Cadence Xcelium, Uvm, systemverilog, Synopsys VCS, AMBA AXI, CPF, UPF

rtl verification , Pcie, Nvme, systemverilog, Uvm, Axi, AHB, Asic verification

Vcs, Jtag, Pcie, Awk, I2c, Python, Jasper, Sed, Perl, Networking Protocols, Ethernet, PLLs, Uvm, Co-Simulations, GLS, AXI4.0, Verdi, debugs, Emulation Platforms, Test Bench Accelerators, Coverage Driven Methodology, systemverilog, Ate, HW SW Flow

C++, Soc, Communication engineering, Simulation, Asic verification, Uvm

Perl, Bash, Python, Tcl, C, shell scripting, simulation and emulation environments, verification methodologies, Linux Unix environment, SystemVerilog UVM, test plan creation and execution

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

Tcl, C, Perl, Verilog, Python, Emulation, Zebu, Veloce, Palladium, Hybrid Simulation, Uvm, systemverilog