Shell, System Verilog, Python, Vcs, Perl, Gdb, RTL, Uvm, Debussy, Asic verification

Makefile, C, Systemc, Windows, Linux, Verilog, Shell, Ruby, System Verilog, Perl, graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, HLS tools, UVM testbenches, TLM, UVM based verification frameworks, simulation profile efficiency improvement