rtl development , power delivery , Verilog, ASIC design flow, Dft, mixed-signal chips, Behavioral Circuit Modeling, Timing Analysis, Custom Digital Design, power management solutions, System-Verilog

rtl development , Jtag, Verilog, I2c, ASIC design flow, Timing Analysis, System-Verilog, mixed-signal chips, SPMI, Custom Digital Design, Behavioral Circuit Modeling, Dft, power management solutions

Digital RTL Design, VHDL, Timing Analysis, Low-Power Design Techniques, Logic Synthesis, systemverilog

C, Vcs, Verilog, Perl, spyglass, formal verification, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

C, Vcs, Verilog, Perl, spyglass, formal verification, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

C, Vcs, Verilog, Perl, formal verification, spyglass, Hardware Emulation Platforms, systemverilog, ASIC Design, cdc, Rtl Design, ASIC SoC development cycle, EVE, Veloce

Static timing analysis, Splunk, Unix, AI ML, Linux, Lsf, Python, Bitbucket, Jenkins, Git, DesignSync, EDA Tools, make, GenAI, Convolutional Networks, CI CD process, SW development and debug tools, Design Verification, reinforcement learning, Graph Neural Networks, Dft, Design revision control, Power-aware flows