Fcoe, spyglass, Verilog RTL coding, Synopsys Design Compiler, ASIC debugging, Multi-domain clock synchronization, High performance memory subsystems, High-speed serial interfaces, LEC, Networking protocols Ethernet, Verplex

C, Vcs, Perl, Verilog, spyglass, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, EVE, Veloce, ASIC Design, formal verification

Digital RTL Design, VHDL, Timing Analysis, Logic Synthesis, Low-Power Design Techniques, systemverilog

Counterexample trace analysis, SystemVerilog Assertions, Constraint debugging, Formal property verification, Tcl-based formal tool flows, systemverilog, Reset and clock modeling

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

bist , Verilog, C, Vcs, Python, AHB, microcontroller platforms, Timing Analysis, systemverilog, digital timing constraints, DFT methodologies, Cadence Virtuoso, APB, Axi, ASIC tool flows, Questa, Timing Constraints, high-speed SerDes, ATPG, FPGAs, AMBA, XCelium, SOC interconnect fabrics, Genus Design Compiler, Asic verification, Scan Insertion, ASIC synthesis

code coverage , Verilog, System Verilog, LINT, cdc, AXI protocol, Low power synthesis, Formality, SoC level Synthesis, UPF, Rtl Design, Synthesis, AMBA, Timing Analysis, RTL Coding, AHB, ip development, functional coverage, front-end design tools

Tcl, Mercurial, Svn, DDR, Git, Pcie, Perl, Ethernet, Arm, Python, RISC-V, systemverilog, AMBA, Emulation, Design Verification infrastructure, System Verilog Assertions

System Verilog, Gate Level Simulations, Building test benches from scratch, ASIC verification using UVM