Perl, Python, Tcl, Assertions SVA, high-speed PHY IPs, verification automation frameworks, Uvm, Functional coverage, systemverilog, CI CD verification flows, Constrained-random verification, AI-assisted verification productivity

Jasper, Verilog, System Verilog, Cadence IEV, Synopsys VCS, Synopsys VC-Formal Magellan, Cadence IES, Formal property checking tools, Uvm, Simulation Tools

Verilog, System Verilog, SVA, Synopsys VCS, assertion and coverage-driven verification, Uvm, formal property checking tools, Cadence IES

System Verilog, Verilog, Jasper, Synopsys VCS, Synopsys VC-Formal Magellan, Uvm, Cadence IES, Simulation Tools, Cadence IEV, Formal property checking tools

Verilog, System Verilog, assertion and coverage-driven verification, Synopsys VCS, Cadence IES, formal property checking tools, Uvm, SVA