C, Gnu, Python, System Verilog, Systemc, TLM 2.0, Tasking, PLS Lauterbach, CCI, Uvm, VLAB, T32, Synopsys Virtualizer, ASTC

UVM Test Bench development, power simulation on VCS, script writing in Python, UPF

Perl, Python, RTL debug skills, SV – UVM Assertions based verification, ARM based system architecture, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi

code coverage , System Verilog, Asic verification, Gate level simulations, IP level verification, UVM Verilog, testbench architecture development, testbench component developments, functional coverage