Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Design Verification, Debugging RTL Verilog designs

C, C++, Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, Post-silicon debugging, RTL design and verification flows, Simulation Tools, JTAG protocols, Digital Design, Assembly language programming

DDR, Ethernet, System Verilog, RISC-V cores, SV coverpoints, GIC, CMN, AXI protocol, SMMU, Low-power verification, PCle, Cache and coherency verification, Uvm, UPF, ACE protocol, eMMC, CoreSight, Low-speed peripherals, ARM v8 and v7 cores, Assembly

Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification

Pcie, Regression Testing, Verilog, Ethernet, assertions, Uvm, systemverilog, functional coverage, constrained-random verification

Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog

Perl, Verilog, Python, Cadence Incisive, Xcelium, complex testbenches, Uvm, systemverilog, Synopsys VCS, RTL design concepts, VHDL, formal verification, verification environments, Modelsim

clocking , Ovm, DDR, Pcie, Verilog, Ethernet, Platform bring up in Emulators or Silicon, SOC boot flow, Constrained-random verification environments, Uvm, systemverilog, Power management flows, C SV tests, Low Power Verification, Coverage report generation, System Verilog Assertions, RTL GLS level simulations

code coverage , Verilog, Debugging, FPGA Design, Scripting, Regression Testing, Vcs, systemverilog, Uvm, Testbench Development, Simulation Tools, Functional Verification, Timing Analysis, SoC Verification, Verification Plan, Verdi