Ovm, System Verilog, Uvm, constrained random verification methodologies, FPGA prototyping, FPGA architecture, Pre Silicon Validation Verification

Shell, Perl, Python, PCIe Gen4, Verification Methodologies, CXL 1.x, Uvm, Assertions, systemverilog, SVA, Coverage-Driven Verification

Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification